1. Field of the Invention
The invention relates to electrostatic discharge (ESD) protection for an integrated circuit (IC), and more particularly, to a method for enhancing the ESD protection capability of an ESD protective device provided in an integrated circuit for enhanced protection of the IC against electrostatic discharge.
2. Description of the Background Art
Electrostatic discharge (ESD) is a movement of static electricity from a nonconductive surface, that could cause damage to semiconductors and other circuit components in ICs. A person walking on a carpet, for instance, can carry electrostatic charge in an amount up to several thousands of volts under high humidity conditions, and over 10,000 volts under low humidity conditions. When a IC is touched by a human hand, the electrostatic charge flows from the person's body to the IC, resulting in an ESD having an energy level up to millions of joules (MJ) and a discharge period as short as only a few nanoseconds (ns) or microseconds (.mu.s). As a consequence, the instantaneous power level of the ESD would be as high as several hundreds of kilowatts with an electric current up to several dozens of amperes, which would cause severe damage to the IC. CMOS (complementary metal-oxide semiconductor) logic ICs are especially vulnerable to ESD.
A conventional method of providing ESD protection for an integrated circuit is to include an ESD protective device having an n-type CMOS transistor, in the integrated circuit. The n-type CMOS transistor can be either a gate-grounded NMOS transistor or gate-coupled NMOS transistor. In semiconductor fabrication, the n-type CMOS transistor can be further downsized so as to reduce the overall size and increase the degree of integration of the integrated circuit. However, the conventional ESD protective device, in order to provide adequate ESD protection capability, should be relatively large, thus restricting the downsizing of the integrated circuit. Therefore, a need exists for a new and improved method that allows an ESD protective device to be fabricated at a reduced size, but nonetheless provides adequate ESD protection for the integrated circuit. Moreover, in order to allow cost-effective manufacture of the integrated circuit, the new and improved method preferably should be carried out without having to devise or include additional process steps in the overall fabrication process for the integrated circuit.